Semiconductor device, semiconductor memory, photoelectric conversion device, moving unit, manufacturing method of photoelectric conversion device, and manufacturing method of semiconductor memory

ABSTRACT

A semiconductor device has a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor is arranged in an active region of a semiconductor substrate, and a gate electrode and the active region overlap with each other in a plan view and also have a portion located between the source and the drain of the first transistor of the semiconductor substrate. In the channel width direction, an impurity concentration of the second conductivity type is higher at the end than on the center side of the portion.

BACKGROUND OF THE INVENTION Field of the Invention

The aspect of the embodiments relates to a semiconductor device, asemiconductor memory, a photoelectric conversion device, a moving unit,a manufacturing method of the photoelectric conversion device, and amanufacturing method of the semiconductor memory.

Description of the Related Art

Japanese Patent Application Laid-Open No. 2000-058675 discloses atechnology to ensure circuit operation stability by using differentthresholds of transistors in a Static Random Access Memory (SRAM)-typesemiconductor memory. Further, Japanese Patent Application Laid-Open No.2017-069231 discloses that the shape of a gate electrode or the filmthickness of a gate insulation film is changed in order to reduce noiseof a transistor.

SUMMARY OF THE INVENTION

One aspect of the embodiments is a memory having a Static Random AccessMemory (SRAM)-type unit cell including a first transistor of a firstconductivity type and a second transistor of a second conductivity type,the first transistor is arranged in an active region of a semiconductorsubstrate, the active region overlaps with a gate electrode of the firsttransistor and includes a portion located between a source and a drainof the first transistor, the portion is arranged across a firstposition, a second position, and a third position aligning in orderalong a channel width direction of the first transistor, the portionincludes a first semiconductor region of the second conductivity typearranged in the first position and a second semiconductor region of thesecond conductivity type arranged in the second position, and theimpurity concentration of the first semiconductor region is higher thanthe impurity concentration of the second semiconductor region.

Another aspect of the embodiments is a method of a semiconductor memoryhaving a Static Random Access Memory (SRAM)-type unit cell including afirst transistor of the first conductivity type and a second transistorof the second conductivity type, and the method includes preparing asemiconductor substrate having a first region and a second region,forming the first groove in the first region and a second groove in thesecond region by using a first mask pattern, forming a second maskpattern having an opening, on the first mask pattern, that covers thefirst groove and exposes the second groove, performing implantation ofimpurity ions of the first conductivity on the semiconductor substratevia the second groove by using the first mask pattern and the secondmask pattern, forming a first element isolation portion having the firstgroove and a second element isolation portion having the second grooveby embedding an insulator in the first groove and the second groove, andforming the first transistor in the first region and the secondtransistor in the second region.

Another aspect of the embodiments is a method of a semiconductor memoryhaving a Static Random Access Memory (SRAM)-type unit cell including afirst transistor of the first conductivity type and a second transistorof the second conductivity type, and the manufacturing method includespreparing a substrate having a first region and a second region, formingthe first groove in the first region and a second groove in the secondregion by using a first mask pattern, forming a second mask patternhaving an opening, on the first mask pattern, that covers the firstgroove and exposes the second groove, performing implantation ofimpurity ions of the first conductivity on the semiconductor substratevia the second groove by using the first mask pattern and the secondmask pattern, forming a first element isolation portion having the firstgroove and a second element isolation portion having the second grooveby embedding an insulator in the first groove and the second groove, andforming the first transistor in the first region and the secondtransistor in the second region.

Another aspect of the embodiments is a semiconductor device having aCMOS circuit including a first transistor of a first conductivity typeand a second transistor of a second conductivity type, the firsttransistor is arranged in an active region of a semiconductor substrate,the first transistor has a portion at which a gate electrode of thefirst transistor and the active region overlap with each other and thatis located between the source and the drain of the first transistor ofthe semiconductor substrate, in the portion, a first semiconductorregion of the second conductivity type is arranged at a first positionand a second semiconductor region of the second conductivity type isarranged at a second position that is between the first position and athird position along a channel width direction of the first transistor,and the impurity concentration of the first semiconductor region ishigher than the impurity concentration of the second semiconductorregion.

Yet another aspect of the embodiments has a unit cell portion in which aunit cell having a photoelectric conversion element is arranged and areadout unit used for reading out a signal from the unit cell portion,the readout unit has at least one first transistor of the firstconductivity type, the first transistor is arranged in an active regionof a semiconductor substrate, the active region overlaps with a gateelectrode of the first transistor and includes a first portion locatedbetween a source and a drain of the first transistor, the first portionis arranged across a first position, a second position, and a thirdposition aligned in order along a channel width direction of the firsttransistor, the first portion includes a first semiconductor region ofthe second conductivity type arranged at the first position and a secondsemiconductor region of the second conductivity type arranged at thesecond position, and the impurity concentration of the firstsemiconductor region is higher than the impurity concentration of thesecond semiconductor region.

Further features of the disclosure will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram illustrating a unit cell of asemiconductor memory according to a first embodiment.

FIG. 2 is a schematic plan view illustrating the unit cell of thesemiconductor memory according to the first embodiment.

FIG. 3A is a schematic sectional view of a transistor according to thefirst embodiment.

FIG. 3B is a schematic sectional view of the transistor according to thefirst embodiment.

FIG. 3C is a diagram illustrating an impurity concentration of thetransistor according to the first embodiment.

FIG. 4A is a schematic sectional view illustrating a manufacturingmethod of a photoelectric conversion device according to a secondembodiment.

FIG. 4B is another schematic sectional view illustrating themanufacturing method of the photoelectric conversion device according tothe second embodiment.

FIG. 4C is yet another schematic sectional view illustrating themanufacturing method of the photoelectric conversion device according tothe second embodiment.

FIG. 5A is a schematic sectional view illustrating the manufacturingmethod of the photoelectric conversion device according to the secondembodiment.

FIG. 5B is another schematic sectional view illustrating themanufacturing method of the photoelectric conversion device according tothe second embodiment.

FIG. 5C is yet another schematic sectional view illustrating themanufacturing method of the photoelectric conversion device according tothe second embodiment.

FIG. 6A is a schematic sectional view illustrating the manufacturingmethod of the photoelectric conversion device according to the secondembodiment.

FIG. 6B is another schematic sectional view illustrating themanufacturing method of the photoelectric conversion device according tothe second embodiment.

FIG. 7 is a schematic sectional view illustrating a manufacturing methodof a photoelectric conversion device according to a third embodiment.

FIG. 8 is a schematic sectional view illustrating a photoelectricconversion device according to a fourth embodiment.

FIG. 9A is a schematic sectional view of a transistor according to afifth embodiment.

FIG. 9B is a diagram illustrating an impurity concentration of thetransistor according to the fifth embodiment.

FIG. 10 is a block diagram illustrating a configuration of aphotoelectric conversion device.

FIG. 11 is an equivalent circuit diagram illustrating a photoelectricconversion device according to the fifth embodiment.

FIG. 12 is an equivalent circuit diagram illustrating a photoelectricconversion device according to a sixth embodiment.

FIG. 13 is an equivalent circuit diagram illustrating a photoelectricconversion device according to a seventh embodiment.

FIG. 14 is a table illustrating a photoelectric conversion deviceaccording to an eighth embodiment.

FIG. 15 is an equivalent circuit diagram illustrating a photoelectricconversion device according to a ninth embodiment.

FIG. 16 is a perspective view illustrating a stacked photoelectricconversion device.

FIG. 17 is a diagram illustrating a configuration of an imaging system.

FIG. 18A is a diagram illustrating a configuration of a moving unit.

FIG. 18B is another diagram illustrating the configuration of the movingunit.

FIG. 19 is a diagram illustrating an operation flow of the moving unit.

DESCRIPTION OF THE EMBODIMENTS

Each embodiment will be described below with reference to the drawings.In the description of each embodiment, with respect to the same featuresas those of other embodiments, the description thereof may be omitted.The polarity of an N-type or a P-type in the descriptions below may bechanged. In such a case, the change can be applied by changing thepolarity of a semiconductor region, changing the control signalpotential, or the like. In the descriptions below, electrical connectionmeans connection to a common node. Further, modifications such asinserting another element (a switch, a buffer, or the like) can beappropriately made in a connection relationship between circuitelements.

First Embodiment

FIG. 1 is an equivalent circuit diagram illustrating a unit cell of asemiconductor memory according to the present embodiment. Thesemiconductor memory according to the present embodiment is a StaticRandom Access Memory (hereinafter, referred to as SRAM). In the SRAM, aunit cell 100 is a bit cell that holds a signal of one bit. A pluralityof unit cells 100 are arranged in the SRAM.

Each unit cell 100 has at least six transistors M1 to M6. Each of thetwo transistors M1 and M2 is a P-type MOS transistor and may function asa transistor for loading (load transistor) of the SRAM. Each of twotransistors M3 and M4 is an N-type MOS transistor and may function as atransistor for driving (driver transistor) of the SRAM. Each of twotransistors M5 and M6 is an N-type MOS transistor and may function as atransistor for transferring (transfer transistor) of the SRAM.Respective transistors are connected as described below.

The sources of the two transistors M1 and M2 are electrically connectedto a node VDD of the power source voltage. The sources of the twotransistors M3 and M4 are electrically connected to a node GND of aground power source voltage. The two transistors M1 and M3 of differentpolarities form one inverter, and the two transistors M2 and M4 ofdifferent polarities form one inverter. Specifically, the drain of thetransistor M1 and the drain of the transistor M3 are electricallyconnected to each other, and gate electrodes of the transistor M1 andthe transistor M3 are electrically connected to each other. In the samemanner, the drain of the transistor M2 and the drain of the transistorM4 are electrically connected to each other, and gate electrodes of thetransistor M2 and the transistor M4 are electrically connected to eachother. Further, these two inverters form one flip-flop. The gateelectrode of the transistor M1 and the drain of the transistor M2 areelectrically connected to each other, and the gate electrode of thetransistor M2 and the drain of the transistor M1 are electricallyconnected to each other.

The transistor M5 may control conduction between one flip-flop and onebit line BL. The transistor M6 may control conduction between oneflip-flop and one bit line BLB. Gate electrodes of the two transistorsM5 and M6 are electrically connected to one word line WL. In the firstembodiment, these six transistors form the unit cell 100 of the SRAM.

FIG. 2 is a schematic plan view illustrating the unit cell 100corresponding to FIG. 1. FIG. 2 illustrates arrangement of thetransistors projected onto the surface of a semiconductor substrate. Thesurface of the semiconductor substrate has an X-direction and aY-direction that is orthogonal to the X-direction. The unit cells 100are arranged in two regions 210 and 220. The region 210 is a region inwhich an N-type semiconductor region is provided, and the region 220 isa region in which a P-type semiconductor region is provided. Thesesemiconductor regions may correspond to a well. The region 210 isarranged with the two transistors M1 and M2, and the region 220 isarranged with the four transistors M3 to M6.

In the region 210, an element isolation region 211 and an active region212 are provided on the surface of the semiconductor substrate. In FIG.2, the transistor M1 is arranged in one active region 212, and thetransistor M2 is arranged in another active region 212. However, thetransistors M1 and M2 may be arranged in the same active region 212. Thetransistor M1 has a gate electrode 231 and P-type semiconductor regions250 and 251 that are the source and the drain. The transistor M2 has agate electrode 230 and P-type semiconductor regions 252 and 253 that arethe source and the drain.

In the region 220, an element isolation region 221 and an active region222 are provided on the surface of the semiconductor substrate. In FIG.2, the transistors M3 and M5 are arranged in one active region 222, andthe transistors M4 and M6 are arranged in another active region 222.However, the transistors M3 to M6 may be arranged in the same activeregion 222. The transistor M3 has the gate electrode 231 and N-typesemiconductor regions 254 and 255 that are the source and the drain. Thetransistor M4 has the gate electrode 230 and N-type semiconductorregions 256 and 257 that are the source and the drain. The transistor M5has a gate electrode 232 and N-type semiconductor regions 255 and 258that are the source and the drain. The transistor M6 has the gateelectrode 232 and N-type semiconductor regions 256 and 259 that are thesource and the drain. Here, the gate electrode 232 functions as the gateelectrodes of the transistors M5 and M6 and may function as the wordline WL in FIG. 1. Here, the example of FIG. 2 lists ACT denoting anactive region, GATE denoting a gate electrode, FIELD denoting an elementisolation region, and CNT denoting a location of a contact plug.

The gate electrodes 230, 231, and 232 are formed of polysilicon, forexample, and may function as a gate electrode of a transistor in aportion overlapping with the active regions 212 and 222. Here, the gateelectrode 231 is arranged commonly to the two transistors M1 and M3, thegate electrode 230 is arranged commonly to the two transistors M2 andM4, and the gate electrode 232 is arranged commonly to the twotransistors M5 and M6. The gate electrodes 230 and 231 extend from theelement isolation region 211 to the active region 212, the elementisolation region 211, the element isolation region 221, the activeregion 222, and the element isolation region 221. The source or thedrain other than the gate electrodes may also be formed of a singlesemiconductor region when the source or the drain of each transistorform a common node.

Here, increased integration of unit cells of the SRAM will be described.The unit cells are arranged repeatedly in the SRAM. By reducing the areaof the unit cell as much as possible, higher integration of the SRAM canbe achieved. To reduce the area of the unit cell, it is effective toreduce the size of a transistor forming the unit cell. To stabilize theoperation as the SRAM, however, a current ratio of respectivetransistors is to be set to a desirable value, and therefore all thetransistors forming the unit cell cannot be formed in the minimum size.If all the transistors forming the unit cell were formed in the minimumsize, the current ratio would change, and thereby reduction in a writingor reading operation rate or an operation failure may occur. Out of thetransistors forming the unit cell, by designing the size of the loadtransistor to be the smallest, the size of other transistors can also bereduced, and a desired current ratio is achieved resulting in a stableoperation. That is, controlling a channel width defining the size of theload transistor to the minimum value is an effective way to reduce thearea of the unit cell. Here, the width of the channel of a transistor isgenerally defined as a width of an active region between elementisolation portions. A space used for element isolation is thus definedin accordance with rules of a semiconductor process. Accordingly, in thepresent embodiment, a semiconductor region having the conductivityopposite to the polarity of the load transistor is provided at theperiphery of an element isolation portion in which the load transistoris provided. By providing such a semiconductor region, an effectivechannel width of a transistor can be smaller than the space of anelement isolation portion. Therefore, design values of the channelwidths of the drive transistor and the transfer transistor can berelatively smaller than in a case where the channel width of the loadtransistor is the minimum value defined by the rules of the process.Thus, the area of the unit cell can be reduced.

Specific configuration of the transistors of the present embodiment willbe described by using FIG. 3A to FIG. 3C. FIG. 3A and FIG. 3B areschematic sectional views of the transistor M1 that is the loadtransistor. FIG. 3A and FIG. 3B are schematic diagrams in which featuressuch as a contact plug are omitted, which are the schematic diagrams inwhich a portion of transistors is focused on. FIG. 3A illustrates across-section of the transistor M1 taken along the X-direction in FIG. 2and illustrates a cross-section of the transistor M1 in the channellength direction. In FIG. 3A, the semiconductor regions 250 and 251 ofthe transistor M1 and the gate electrode 231 provided on a gateinsulating film 602 are illustrated. The transistor M1 is provided in anN-type semiconductor region 58 b. The transistor M1 has a portion 601located between the semiconductor region 250 and the semiconductorregion 251. The portion 601 is a portion in which the gate electrode 231and the active region 212 overlap with each other in a plan view.

FIG. 3B illustrates a cross-section of the transistor M1 taken along theY-direction in FIG. 2, which is a cross-section of the transistor M1 inthe channel width direction. The active region 212 in which thetransistor M1 is arranged between the two element isolation regions 211is arranged. An element isolation portion 31 is provided to the elementisolation region 211. The element isolation portion 31 has a trenchisolation structure to which an insulator formed at a groove (trench) isarranged, for example. The trench isolation structure may be ShallowTrench Isolation (STI) structure or Deep Trench Isolation (DTI)structure. In the present embodiment, the element isolation portion 31is the STI. The gate electrode 231 extends from the element isolationregion 211 to the active region 212. The gate electrode 231 extends fromthe top of the element isolation portion 31 to the top of the gateinsulating film 602. Here, the portion 601 is the active region 212 withwhich the gate electrode 231 is overlapped in the Z-direction. Theportion 601 is a region in which a channel of a transistor may betypically formed.

In the present embodiment, an N-type semiconductor region 52 is providedalong the side face and the bottom face of a groove of the elementisolation portion 31. The N-type semiconductor region 52 has a higherimpurity concentration than the N-type semiconductor region 58 b. InFIG. 3B, the semiconductor region 52 is denoted with n+, and thesemiconductor region 58 b is denoted with n. Due to the N-typesemiconductor region 52, the channel width that may be actually formed,that is, the effective channel width of the transistor M1 is reduced.When the width between the element isolation regions 31, that is, thewidth of the portion 601 is a width W1, the effective channel width isW2. It can also be said that the effective channel width is defined bythe semiconductor region 52. For example, when the width W1 is largerthan or equal to 80 nm and smaller than or equal to 120 nm, the width W2can be larger than or equal to 60 nm and smaller than or equal to 100nm, for example. The width W2 is not limited to these values and can beappropriately set in accordance with the semiconductor region 52.

A line section AB in FIG. 3B is a line section along the gate widthdirection and is located at the ends of the portions 601. The linesection AB has a position P1, a position P2, and a position P3 on theline section. The position P2 is a position between the position P1 andthe position P3. The semiconductor regions 52 are provided to theposition P1 and the position P3, and the semiconductor region 58 b isprovided to the position P2. FIG. 3C is a diagram illustrating theimpurity concentration of the N-type semiconductor regions in the linesection AB in FIG. 3B. Here, the impurity concentration refers to a NETconcentration. While it is assumed that the position P1 and the positionA are the same position and the position P3 and the position B are thesame position in FIG. 3B, the positions P1 to P3 are present between theposition A and the position B in an actual implementation. Theconcentration at the position P1 is denoted as C1, the concentration atthe position P2 is denoted as C2, and the concentration at the positionP3 is denoted as C3. At this time, C1=C3>C2 is obtained. That is, it canbe seen that the impurity concentration increases from the center partof the portion 601 toward the boundary between the element isolationportion 31 and the portion 601.

With such a configuration, when the gate electrode 231 is controlled toan on-state, the channel is formed at the position P2, and no channel isformed at the position P1 or the position P3. That is, the threshold ofthe transistor at the position P1 or the position P3 is higher than thatof the position P2. Therefore, the effective channel width of thetransistor is reduced with respect to the space between the elementisolation portions. With such an impurity concentration profile, theeffective channel width can be formed smaller than the space between theelement isolation portions 31.

In the present embodiment, while the concentration C1 and theconcentration C3 are the same concentration, concentrations differentfrom each other may be used. Further, in the present embodiment, theconcentration C1 and the concentration C3 are to be twice or more theconcentration C2. The concentration C1 and the concentration C3 are more10 times or more the concentration C2. With such a concentrationrelationship, the effective channel width is ensured to be reduced in anoperation voltage range.

Note that, in the present embodiment, while it has been described thatthe semiconductor region 58 b in the portion 601 is the N-type, a P-typemay also be used as long as the transistor M1 is configured to operate.That is, out of the impurity concentrations of the positions P1, P2, andP3, donor concentrations are D1, D2, and D3, and acceptor concentrationsare A1, A2, and A3, respectively. Here, the concentrations D1, D2, D3,A1, A2, and A3 each have a value larger than or equal to zero. At thistime, the concentration relationship at each position is D1−A1>D2−A2,and D3−A3>D2 A2.

Further, the position P1 is between the side face of the trench of theelement isolation portion 31 and the position P2 and can also be said tobe adjacent to the element isolation portion 31. The position P3 isbetween the side face of the trench of the element isolation portion 31and the position P2 and can also be said to be adjacent to the elementisolation portion 31. In the present embodiment, at the depth of theline section AB, the semiconductor region 52 extends from the side faceof the trench to a position of 20 nm, for example.

While being applied to the load transistor of the SRAM-typesemiconductor memory, the present embodiment may be applied to othertransistors in accordance with the characteristics. By applying atransistor having such a configuration to an SRAM-type semiconductormemory, it is possible to reduce of the size of the unit cell.

Second Embodiment

In the present embodiment, a photoelectric conversion device 300 usingthe semiconductor memory of the first embodiment will be described. Inthe photoelectric conversion device of the present embodiment, an SRAMand a photoelectric conversion unit having a photoelectric conversionelement are arranged on the same semiconductor substrate. Here, thephotoelectric conversion unit may be a CCD sensor, a CMOS sensor, or thelike. The photoelectric conversion unit of the present embodiment is aCMOS sensor having a photodiode that is a photoelectric conversionelement, a transfer transistor, and an amplification transistor.

A manufacturing method of the photoelectric conversion device of thepresent embodiment will be described by using FIG. 4A to FIG. 6B. FIG.4A to FIG. 6B are schematic sectional views illustrating themanufacturing method of the photoelectric conversion device 300. Aregion 310 is a region in which the SRAM is formed and includes theregions 210 and 220 described in the first embodiment. A region 330 is aregion in which a pixel of the photoelectric conversion unit isarranged. The pixel includes at least a photodiode and a transfertransistor. A processing circuit unit including a circuit for operatinga pixel or a circuit for signal processing is arranged in a region 340.The processing circuit unit includes a logic circuit or the like, forexample, and is also referred to as a peripheral circuit in an imagingdevice. The region 340 has a region 350 and a region 360. The region 350represents a region in which an N-type transistor is arranged, and theregion 360 represents a region in which a P-type transistor is arranged.

A process illustrated in FIG. 4A will be described. First, a substrate30 is prepared. The substrate 30 is a single-crystal substrate ofsilicon, for example, and may be a processed substrate. The substrate 30has the region 310, the region 330, and the region 340. Next, a maskpattern 32 is formed on the substrate 30. The mask pattern 32 is a maskpattern used for forming a groove to be an element isolation portion.The mask pattern 32 has openings provided at any positions in the region220, the region 210, the region 330, and the region 340, respectively.The openings of the mask pattern 32 expose portions in which grooves areto be formed later on the surface S1 of the substrate 30. Then, byetching the substrate 30 by using the mask pattern 32 as a mask, grooves31 a to 31 d corresponding to respective openings are formed. The groove31 a is provided in the region 220, the groove 31 b is provided in theregion 210, the groove 31 c is provided in the region 330, and thegroove 31 d is provided in the region 340. Here, the mask pattern 32 isformed of, for example, an inorganic material such as a silicon nitridefilm, a silicon oxide film, or the like. The mask pattern 32 can beformed by forming an inorganic material film on the substrate 30,forming a pattern made of an organic material on the inorganic materialfilm, and removing a part of the inorganic material film by etching byusing the pattern as a mask. In the present embodiment, a siliconnitride film is used as an inorganic material. The pattern made of anorganic material may be a photoresist pattern, for example.

In FIG. 4B, a mask pattern 33 is formed on the mask pattern 32. The maskpattern 33 is a mask pattern used for forming an N-type semiconductorregion on the side face and the bottom face of the groove of the region210. The mask pattern 33 covers the regions 220, 330, and 340 andexposes the region 210. That is, the mask pattern 33 covers the grooves31 a, 31 c, and 31 d and exposes the groove 31 b. The mask pattern 33has an opening 51 that exposes the region 210. The opening 51 may exposeat least the groove 31 b of the region 210. Here, as described in thefirst embodiment, the region 210 is a portion in which the loadtransistor of the SRAM is formed and a region in which a P-typetransistor is formed. The mask pattern 33 is formed of a photoresist.The mask pattern 33 is formed by performing exposure, development, orthe like after forming a film made of a photoresist on the mask pattern32. Ion implantation 40 is then performed on the substrate 30 by usingthe mask pattern 32 and the mask pattern 33 as a mask. The N-typesemiconductor region 52 is formed along the side face and the bottomface of the trench by the ion implantation 40. Ion species of the ionimplantation 40 are impurity ions used for forming an N-typesemiconductor region such as phosphorus (P), arsenic (As), or the like,for example. Any implantation angle for the ion implantation 40 may beselected. In the present embodiment, the ion implantation is appliedobliquely to the surface S1 of the substrate 30, and it is to select theion implantation angle of around 10 degrees. Here, the ion implantationangle is an angle formed between the perpendicular line of the surfaceS1 and the direction of the ion implantation. With such an implantationangle, ions can be effectively implanted even on the side face of atrench. Further, by performing the ion implantation 40 with rotation of360 degrees in the direction on the surface S1, the ion implantation canbe performed on the entire side face of a trench. Subsequently, the maskpattern 32 is left, and the mask pattern 33 is removed (notillustrated).

In FIG. 4C, a mask pattern 34 is formed on the mask pattern 32. The maskpattern 34 is a mask pattern used for forming a P-type semiconductorregion on the side face and the bottom face of the groove of the region330. The mask pattern 34 covers the regions 210, 220, and 340 andexposes the region 330. That is, the mask pattern 34 covers the grooves31 a, 31 b, and 31 d and exposes the groove 31 c. The mask pattern 34has an opening 53 that exposes the region 330. The opening 53 may exposeat least the groove 31 c of the region 330. The mask pattern 34 isformed of a photoresist. The mask pattern 34 is formed by performingexposure, development, or the like after forming a film made of aphotoresist on the mask pattern 32. Ion implantation 41 is thenperformed on the substrate 30 by using the mask pattern 32 and the maskpattern 34 as a mask. The P-type semiconductor region 54 is formed alongthe side face and the bottom face of the trench by the ion implantation41. Ion species of the ion implantation 41 are impurity ions used forforming a P-type semiconductor region such as boron (B), boron fluoride(BF₂), or the like, for example. Any implantation angle for the ionimplantation 41 may be selected, and it is to select the angle of around10 degrees with respect to the surface S1 of the substrate 30. With suchan implantation angle, ions can be effectively implanted even on theside face of a trench. Further, by performing the ion implantation 41with rotation of 360 degrees in the direction on the surface S1, the ionimplantation can be performed on the entire side face of a trench.

Subsequently, the mask pattern 32 is left, and the mask pattern 34 isremoved. The mask pattern 32 is then removed, and an insulator isembedded to the groove 31 a to the groove 31 d to form an elementisolation portion. The insulator may be, for example, silicon oxide orsilicon nitride. First, the mask pattern 34 is removed, and a heatingprocess is then performed to reduce damage occurring at the groovesbefore a film of an insulator is formed, for example. At this time, afilm caused by thermal oxidation may be formed on the inner wall of thegroove. The element isolation portion 31 is formed by forming a film ofan insulator so as to cover the groove 31 a to the groove 31 d by usinga high-density plasma CVD method or the like and removing an excessiveinsulator film by using a polishing technology such as etching, a CMPmethod, or the like. The element isolation portion 31 in which thesemiconductor region 52 is formed on the periphery is formed in theregion 210, and the element isolation portion 31 in which thesemiconductor region 54 is formed on the periphery is formed in theregion 330. Neither the semiconductor regions 52 nor 54 is formed on theperiphery of the element isolation portions 31 in the region 220 and theregion 340. Further, a film of silicon oxide is formed on the surface S1for a subsequent process (not illustrated).

In FIG. 5A, a mask pattern 35 is formed on the surface S1 of thesubstrate 30. The mask pattern 35 is a mask pattern used for formingP-type semiconductor regions in the region 220, the region 330, and theregion 350. These P-type semiconductor regions may function as a well inwhich an element is formed, for example. The mask pattern 35 covers theregions 210 and the region 360 and exposes the region 320, the region330, and the region 350. That is, the mask pattern 35 has openings 55 a,55 c, and 55 d that expose the region 320, the region 330, and theregion 350. The mask pattern 35 is formed of a photoresist and formed inthe same manner as other mask patterns. Ion implantation 42 is thenperformed to the substrate 30 by using the mask pattern 35 as a mask. AP-type semiconductor regions 56 a, 56 c, and 56 d are formed by the ionimplantation 42. Ion species of the ion implantation 42 are the same asthose of the ion implantation 41. Any implantation angle for the ionimplantation 42 may be selected. Note that, since the region 330 is aregion in which a photoelectric conversion element is formed, in orderto form the well suitable for the photoelectric conversion element,additional ion implantation may be performed, or the region 330 may beformed in a different process from the process for the regions 220 and340. Subsequently, the mask pattern 35 is removed (not illustrated).

In FIG. 5B, a mask pattern 36 is formed on the surface S1 of thesubstrate 30. The mask pattern 36 is a mask pattern used for formingN-type semiconductor regions in the region 210 and the region 360. TheN-type semiconductor regions may function as a well in which an elementis formed, for example. The mask pattern 36 covers the regions 220, theregion 330, and the region 350 and exposes the region 210 and the region360. The mask pattern 36 has openings 57 b and 57 d that expose theregion 210 and the region 360. The mask pattern 36 is formed of aphotoresist and formed in the same manner as other mask patterns. Ionimplantation 43 is then performed on the substrate 30 by using the maskpattern 36 as a mask. N-type semiconductor regions 58 b and 58 d areformed by the ion implantation 43. Ion species of the ion implantation43 are the same as those of the ion implantation 40. Any implantationangle for the ion implantation 43 may be selected. Subsequently, themask pattern 36 is removed (not illustrated).

In FIG. 5C, a mask pattern 37 is formed on the surface S1 of thesubstrate 30. The mask pattern 37 is a mask pattern used for forming aP-type semiconductor region 60 in the region 210. The P-typesemiconductor region 60 may be provided for adjusting the threshold ofthe transistor. The mask pattern 37 covers the regions 220, the region330, and the region 340 and exposes the region 210. The mask pattern 37has an opening 59 that exposes the region 210. The mask pattern 37 isformed of a photoresist and formed in the same manner as other maskpatterns. Ion implantation 44 is then performed on the substrate 30 byusing the mask pattern 37 as a mask. The P-type semiconductor region 60is formed by the ion implantation 44. Ion species of the ionimplantation 44 are the same as those of the ion implantation 41. Anyimplantation angle for the ion implantation 44 may be selected.Subsequently, the mask pattern 37 is removed (not illustrated).

In FIG. 6A, a mask pattern 38 is formed on the surface S1 of thesubstrate 30. The mask pattern 38 is a mask pattern used for forming anN-type semiconductor region 62 in the region 220. The N-typesemiconductor region 62 may be provided for adjusting the threshold ofthe transistor. The mask pattern 38 covers the regions 210, the region330, and the region 340 and exposes the region 220. The mask pattern 38has an opening 61 that exposes the region 220. The mask pattern 38 isformed of a photoresist and formed in the same manner as other maskpatterns. Ion implantation 45 is then performed on the substrate 30 byusing the mask pattern 38 as a mask. The N-type semiconductor regions 62is formed by the ion implantation 45. Ion species of the ionimplantation 45 are the same as those of the ion implantation 40. Anyimplantation angle for the ion implantation 45 may be selected.Subsequently, the mask pattern 38 is removed (not illustrated).

Here, in general, a circuit formed in the region 340 uses a transistorhaving a low threshold to increase the operation speed. On the otherhand, a circuit formed in the region 310 or an SRAM uses a transistorhaving a relatively high threshold to stabilize the circuit operation.Accordingly, in the present embodiment, addition of the processesillustrated in FIG. 5C and FIG. 6A makes it possible to make thetransistors in the region 310 and the region 340 in a single process.With such a manufacturing method, it is possible to manufacture aphotoelectric conversion device at low cost. Note that, the processillustrated in FIG. 5C or FIG. 6A may be applied to the transistor inthe region 330 or the region 340.

FIG. 6B illustrates a state where an element is formed after the processdescribed in FIG. 6A. A P-type transistor is formed in the region 210,an N-type transistor is formed in the region 220, an N-type transistor,a photoelectric conversion element, or the like is formed in the region330, and an N-type transistor and a P-type transistor are formed in theregion 340. The transistors or the photoelectric conversion element canbe formed by formation of a gate electrode or ion implantation. Then, aphotoelectric conversion device is formed by forming an interlayerinsulating film, a contact plug, or a wiring layer and forming a colorfilter, a micro-lens, or the like. Note that, for a photoelectricconversion device of a backside illumination type, thinning of thesubstrate 30, forming an element isolation on the backside, or the likemay be performed. As described above, a photoelectric conversion deviceis formed in the processes illustrated in FIG. 4A to FIG. 6B.

Here, the condition of ion implantation in accordance with thecharacteristics of the transistor of the region 210 will be described.The characteristics of the transistor are significantly affected by theion implantation 40 and the ion implantation 44. Here, a dose of the ionimplantation 40 is larger than a dose of the ion implantation 44. Thisis because the impurity concentration relationship described above issatisfied. With such a manufacturing method, no channel is formed in thesemiconductor region 52 located under the gate electrode of thetransistor, and thereby the effective channel width of the transistorcan be reduced.

Note that, the mask pattern 32 illustrated in FIG. 4A may be formed of aphotoresist. In such a case, ultraviolet irradiation is performed on themask pattern 32 formed of a photoresist to cure the photoresist, forexample. By forming the mask pattern 32 formed of a photoresist in sucha way, it is possible to remove the mask pattern 33 in the process ofFIG. 4B while leaving the mask pattern 32. Note that, by forming themask pattern 32 of a photoresist, time for dry etching or the like toremove the mask pattern 32 can be reduced compared to a case where themask pattern 32 is formed of an inorganic material.

Third Embodiment

In the present embodiment, a modified example of the photoelectricconversion device 300 using the semiconductor memory of the secondembodiment will be described by using FIG. 7. FIG. 7 is a schematicsectional view illustrating a manufacturing method of a photoelectricconversion device of the present embodiment.

In the present embodiment, the polarity of the photoelectric conversionelement of the second embodiment is changed. That is, the semiconductorregion 54 in FIG. 6B is an N-type semiconductor region that is the samepolarity as the semiconductor region 52. With such a configuration, asillustrated in FIG. 7, the processes of forming the semiconductor region52 and the semiconductor region 54 can be performed in a single process.The processes of forming include a process of a mask pattern formationor a process of ion implantation. According to the present embodiment, aphotoelectric conversion device having an SRAM can be formed by usingfewer processes.

Fourth Embodiment

In the present embodiment, a modified example of the photoelectricconversion device 300 using the semiconductor memory of the secondembodiment will be described. FIG. 8 is a schematic sectional view of aphotoelectric conversion device of the present embodiment. In thepresent embodiment, an N-type semiconductor region 801 is provided to atransistor in the region 360. The semiconductor region 801 has the samefunction as the semiconductor region 52 of the second embodiment. Such aconfiguration can provide a finer transistor. Further, the presenttransistor configuration reduces noise such as Random Telegraph Noise(hereinafter, referred to as RTN) or the like due to a channel of atransistor. The present embodiment can be applied to a CMOS circuit thatis a circuit in which the RTN is to be considered in addition to thephotoelectric conversion device.

Fifth Embodiment

In the present embodiment, a photoelectric conversion device to whichtransistors are applied will be described. Before the description of thephotoelectric conversion device, a transistor with reduced noise will bedescribed in detail by using FIG. 3A to FIG. 3C and FIG. 9A to FIG. 9B.

FIG. 9A and FIG. 9B are schematic diagrams illustrating an example of acase without the semiconductor region 52 illustrated in FIG. 3B. FIG. 9Ais a schematic sectional view of a transistor in accordance with FIG.3B. FIG. 9B corresponds to FIG. 3C and is a diagram illustrating theimpurity concentration of an N-type semiconductor region in the linesegment AB in FIG. 9A. In FIG. 9A and FIG. 9B, the same components asthose of FIG. 3A to FIG. 3C are labeled with the same reference, and thedescription thereof will be omitted. A transistor in a comparativeexample illustrated in FIG. 9A does not have the semiconductor region 52illustrated in FIG. 3B. Thus, the impurity concentration in the linesegment AB in FIG. 9A illustrated in FIG. 9B is constant at theconcentration C2. The difference between the maximum and the minimum ofthe impurity concentration change of the P-type semiconductor region 58b in the line segment AB in FIG. 9A is smaller than the differencebetween the maximum and the minimum of the impurity concentration changeof the P-type semiconductor region in the line segment AB in FIG. 3B.The difference between the maximum and the minimum of the impurityconcentration change of the P-type semiconductor region in the linesegment AB in FIG. 3B can be said as the impurity concentrationdifference between the semiconductor region 52 and the semiconductorregion 58 b. Here, the effective channel width of a transistor of thecomparative example is defined as a width W3. While the effectivechannel width of the transistor described in FIG. 3A and FIG. 3B is thewidth W2, the effective channel width of the transistor of thecomparative example is the width W3. The width relationship is W3=W1>W2.In the description below, the transistor illustrated in FIG. 3A and FIG.3B is denoted as a first-type transistor, and the transistor illustratedin FIG. 9A is denoted as a second-type transistor.

An inverse narrow channel effect may occur in a transistor arrangedadjacent to the element isolation portion 31 of the STI structure. Theinverse narrow channel effect means an operation of a transistordescribed below. The channel end along the channel width direction ofthe transistor is adjacent to the STI structure. An electric fieldgenerated by the gate electrode is concentrated at this channel end. Asa result, the threshold of the transistor is reduced at the channel end.Here, when the transistor is driven, the drain current flows. That is,in the configuration in FIG. 9A, the drain current is concentrated atthe channel end having a low threshold. Further, oxygen deficiency isgenerated inside the semiconductor substrate near the element isolationportion 31. In the region having oxygen deficiency, the phenomenon oftrapping or emitting of electrons serving as carriers may frequentlyoccur. When a drain current is concentrated at the channel end, that is,near the element isolation portion 31, the value of RTN increases, thatis, deteriorates. That is, depending on the position at which thesecond-type transistor illustrated in FIG. 9A is used, the RTN issuperimposed on a signal. In a case of a photoelectric conversiondevice, such a situation may cause deterioration of the image quality,such as deterioration in which a liner flaw appears in an image due tonoise, for example. The first-type transistor has the improved RTNcharacteristics compared to the second-type transistor, and thesecond-type transistor can be manufactured in a smaller number ofprocesses than the first-type transistor and can improve drive forcebecause the effective channel length is long. Next, the arrangement oftransistors in a photoelectric conversion device will be described.

FIG. 10 is a block diagram illustrating a configuration of aphotoelectric conversion device. A unit cell portion 1000 has aplurality of unit cells 1001. The unit cells 1001 are two-dimensionallyarranged. The unit cell 1001 may be referred to as a pixel in aphotoelectric conversion device. The unit cell 1001 has a pixelconfiguration of a CMOS-type photoelectric conversion device, forexample. A vertical scanning circuit 1002 outputs a control signal usedfor driving each unit cell 1001. A control line 1012 electricallyconnects the vertical scanning circuit 1002 to each unit cell 1001 andsupplies control signals to the element of each unit cell 1001. While asingle control line 1012 is arranged to a plurality of unit cells 1001arranged on each row in FIG. 10, a plurality of control lines 1012 arearranged on each row in the actual implementation. A plurality of linesrefer to the number of lines used to control the unit cells 1001.Signals from the unit cells 1001 are output to a signal line 1013. Atleast one signal line 1013 is electrically connected to a plurality ofunit cells 1001 arranged on each column. The signal line 1013 iselectrically connected to a signal readout unit 1014.

The signal readout unit 1014 has a current source circuit 1003, a signalamplifier circuit 1004, an analog-to-digital (AD) converter circuit1005, and a memory circuit 1007. The current source circuit 1003supplies a constant current used for reading out a signal of the unitcell 1001 to the signal line 1013. The signal line 1013 is electricallyconnected to the signal amplifier circuit 1004. The signal amplifiercircuit 1004 amplifies a signal input from the signal line 1013. The ADconverter circuit 1005 converts an analog signal from the signalamplifier circuit 1004 to a digital signal. A ramp generation circuit1006 generates a reference signal to be compared with a signal on whichAD conversion is performed in the AD converter circuit 1005. A countercircuit 1008 outputs a count value. The memory circuit 1007 holds acount value output from the counter circuit 1008. A horizontal scanningcircuit 1015 supplies a control signal used for transferring a valueheld in the memory circuit 1007 to a signal processing circuit 1010. Asignal output circuit 1011 outputs a signal processed in the signalprocessing circuit 1010 to the outside of the photoelectric conversiondevice. Driving of these circuits is controlled based on control signalsfrom a timing generator (TG) 1009. Note that the circuit such as asignal amplifier circuit 1004, the AD converter circuit 1005, or thelike can be appropriately omitted or changed. Here, a portion in which acircuit other than the unit cell portion 1000 is arranged may bereferred to as a peripheral circuit portion.

FIG. 11 is an equivalent circuit diagram illustrating a photoelectricconversion device. FIG. 11 illustrates a readout path of thephotoelectric conversion device. FIG. 11 illustrates a configuration ofthe unit cell 1001, the current source circuit 1003, the signalamplifier circuit 1004, and the AD converter circuit 1005 illustrated inFIG. 10. The unit cell 1001 includes a photodiode (hereinafter, referredto as PD) 1101, a transfer transistor 1102, a floating diffusion portion(hereinafter, referred to as FD) 1104, a reset transistor 1103, anamplification transistor 1105, and a select transistor 1106. The PD 1101functions as a photoelectric conversion unit that photoelectricallyconverts an incident light received through an optical system. The anodeof the PD 1101 is grounded, and the cathode is connected to the sourceof the transfer transistor 1102. The transfer transistor 1102 is drivenby a control signal TX input to the gate and transfers charges generatedin the PD 1101 to the FD 1104. The FD 1104 temporarily accumulatescharges and functions as a charge-to-voltage converter unit thatconverts accumulated charges into a voltage signal. The amplificationtransistor 1105 forms a source follower amplifier together with thecurrent source circuit 1003. An electric signal charge-to-voltageconverted in the FD 1104 is input to the gate of the amplificationtransistor 1105. Further, the drain of the amplification transistor 1105is connected to a power source voltage VDD, and the source thereof isconnected to the select transistor 1106. The reset transistor 1103electrically connects the FD 1104 to the power source voltage VDD. Whenthe reset transistor 1103 is controlled to an on-state by a controlsignal RES, charges in the FD 1104 are drained to the power sourcevoltage VDD and reset. Here, the power source voltage VDD may bereferred to as a reference voltage. The select transistor 1106electrically connects the amplification transistor 1105 to a signal line1107. When a row of interest is selected at a certain time, a controlsignal SEL is controlled to a high level. The select transistor 1106 towhich the control signal SEL at the high level is supplied is controlledto a conduction state, and a signal from the amplification transistor1105 is output to the signal line 1107. These transistors of the unitcell 1001 are N-type transistors. A constant current is supplied to thesignal line 1107, and a source follower amplifier is formed.

The current source circuit 1003 includes three N-type transistors 1108to 1110. The three transistors 1108 to 1110 are provided between thesignal line 1107 and the ground voltage GND so as to be directlyconnected. The transistor 1109 and the transistor 1110 arecascode-connected and function as a current source. The transistor 1108functions as a switch used for turning on or off the current source. Acontrol signal V1108 is supplied to the gate of the transistor 1108. Inresponse to the control signal V1108 being at the high level, a constantcurrent is supplied to the signal line 1107, and in response to thecontrol signal V1108 being at a low level, the supply of the constantcurrent to the signal line 1107 stops. A control signal V1109 issupplied to the gate of the transistor 1109, and a control signal V1110is supplied to the gate of the transistor 1110. The control signal V1109and the control signal V1110 are fixed bias voltages that determine theoperation points of the transistor 1109 and the transistor 1110,respectively.

The output of the source follower amplifier formed of the amplificationtransistor 1105 is input to the signal amplifier circuit 1004. Thesignal amplifier circuit 1004 includes an inverting amplifier 1112, aninput capacitor 1111, a feedback capacitor 1114, a switch 1113, and aswitch 1115. The degree of amplification of a signal can be changed byselecting or deselecting the feedback capacitor 1114 by using the switch1113 to change the capacitance value. Further, the degree ofamplification of a signal may be changed by changing the position of theswitch 1113 to change the capacitance value of the input capacitor 1111.The switch 1115 resets the inverting amplifier 1112, the input capacitor1111, and the feedback capacitor 1114. A signal amplified by the signalamplifier circuit 1004 is AD-converted in the AD converter circuit 1005.

The relationship between a current flowing in the signal line 1107 and asignal will now be described. First, a change amount ΔVvl of a voltageVvl of the signal line 1107 when a current Ivl flowing in the signalline 1107 changes by ΔIvl is calculated. Where β is a current parameterof the amplification transistor 1105, Vvl and ΔVvl are expressed byEquation (1) and Equation (2).Vvl=Vfd−Vth−√2Ivl/β  Equation (1)ΔVvl=−√2ΔIvl/β  Equation (2)It is understood from Equation (2) that the voltage Vvl changes as thecurrent Ivl of the signal line 1107 changes. That is, the current Ivlcauses a change of the voltage Vvl. Here, since an optical signal fromthe PD 1101 or a reset signal used as a reference appears in the voltageVvl, the voltage Vvl do not vary because of other factors. If thevoltage Vvl varied, the change would be superimposed on a voltageindicating a signal and result in noise. In other words, in oneembodiment, the current Ivl be a constant current that varies less.Accordingly, as described by using FIG. 3A to FIG. 3C and FIG. 9A toFIG. 9B, the first-type N-type transistor having a constant draincurrent be applied to the transistor 1109 and the transistor 1110 thatform the current source. With such a configuration, the current ΔIvl andthe voltage ΔVvl can be reduced, and deterioration of signals due to RTNcan be reduced.

Sixth Embodiment

A photoelectric conversion device according to the present embodimentwill be described by using FIG. 12. FIG. 12 is an equivalent circuitdiagram illustrating the photoelectric conversion device according tothe present embodiment. FIG. 12 illustrates the inverting amplifier 1112of the signal amplifier circuit 1004 illustrated in FIG. 10 or FIG. 11.The inverting amplifier 1112 includes at least five transistors 1201 to1205. The P-type transistor 1202 and the P-type transistor 1203 arecascode-connected to each other to form a current source circuit. Thecurrent source flows a constant current of 6 μA, for example. A controlsignal V1202 and a control signal V1203 are supplied to the gates of thetransistor 1202 and the transistor 1203, respectively, and are fixedbias voltages that determine operation points of respective transistors.The P-type transistor 1201 functions as a switch to turn on or off thecurrent source circuit. A control signal V1201 is supplied to the gateof the transistor 1201 and controls turning on/off of the transistor1201. The N-type transistor 1204 is a gate-grounded transistor. Acontrol signal V1204 is a fixed bias voltage to determine the operationpoint. The N-type transistor 1205 is a source-grounded transistor. Aninput signal Vampi is input to the gate of the transistor 1205 insteadof a control signal. An output signal Vampo of the inverting amplifier1112 is output to a common node of the transistor 1204 and thetransistor 1203.

Here, a gain Ao of the inverting amplifier 1112 is expressed by Equation(3).

$\begin{matrix}{{Ao} = {\frac{Vampo}{Vampi} = {- {gmR}}}} & {{Equation}\mspace{14mu}(3)}\end{matrix}$

Here, the source-grounded N-type transistor 1205 has a mutualconductance gm and an output resistance R. If the RTN deteriorated inthe transistor 1202 or the transistor 1203, the drain current of thetransistor 1205 would change, and the mutual conductance gm of thetransistor 1205 would change. As a result, as described in Equation (3),the gain Ao will change. This means that, if a certain signal wereinput, the signal amplified by a single inverting amplifier 1112 wouldcause variation in the signal magnitude in accordance with the timing(time) of the amplification. Further, with a plurality of invertingamplifiers 1112 being provided, even when a constant signal is input, aplurality of amplified signals may cause variation in the signalmagnitude. It is therefore the first-type transistor of the P-type isapplied to the P-type transistor 1202 and the P-type transistor 1203that form the current source circuit. Further, the control signals V1204and V1205 are input to the transistor 1204 and the transistor 1205 todetermine the operation points to respective gates. Since a change in adrain current causes a change in the operation, in one embodiment, thefirst-type transistor is applied to such transistors. In other words,the first-type transistor of the N-type is applied to the N-typetransistor 1204 and the N-type transistor 1205. As described in thepresent embodiment, by applying the first-type transistor to at leastthe transistor 1202 and the transistor 1203 in the signal amplifiercircuit 1004, it is possible to suppress deterioration of a signal.

Seventh Embodiment

A photoelectric conversion device of the present embodiment will bedescribed by using FIG. 13. FIG. 13 is an equivalent circuit diagramillustrating the photoelectric conversion device of the presentembodiment. FIG. 13 illustrates the AD converter circuit 1005illustrated in FIG. 10 or FIG. 11. The AD converter circuit 1005includes at least a comparator 1300. The comparator 1300 includestransistors 1301 to 1307. The P-type transistor 1301 and the P-typetransistor 1302 are cascode-connected to each other to form a currentsource circuit. The P-type transistor 1303 may function as a switch toturn on or off the current source circuit. A control signal V1303 issupplied to the gate of the transistor 1303 and controls conduction ofthe transistor 1303. The P-type transistor 1304 functions as an inputtransistor. A ramp signal output from the ramp generation circuit 1006illustrated in FIG. 10 is input to the gate of the transistor 1304. TheP-type transistor 1305 functions as an input transistor. The amplifiedsignal Vampo output from the signal amplifier circuit 1004 illustratedin FIG. 10 is input to the gate of the transistor 1305. In FIG. 13, thegate of the transistor 1304 is denoted as an input end INN, and the gateof the transistor 1305 is denoted as an input end INP. The drain of thetransistor 1304 is electrically connected to the drain of the N-typetransistor 1306, and the drain of the transistor 1305 is electricallyconnected to the drain of the N-type transistor 1307. The comparator1300 of such a circuit outputs a result of comparison of the signalvoltage Vampo due to an optical signal and the ramp signal serving asthe reference signal. The output is output to the node to which thetransistor 1305 and the transistor 1307 are connected, which may affectthe comparison result through a capacitor, a latching circuit, and alogic circuit, in response to a change of the current value in thecurrent source circuit. It is thus the first-type transistor is appliedto at least the transistor 1301 and the transistor 1302 of thecomparator 1300. Further, the first-type transistor may be applied tothe transistors 1304 to 1307. As described in the present embodiment, byapplying the first-type transistor to at least the transistor 1202 andthe transistor 1203 in the AD converter circuit 1005, it is possible tosuppress deterioration of a signal.

Eighth Embodiment

In each of the fifth to seventh embodiments, in the photoelectricconversion device, details of the circuit in which the first-typetransistor is provided have been described. In the present embodiment, aportion of the photoelectric conversion device to which the first-typetransistor is provided will be described. FIG. 14 is a tableillustrating a photoelectric conversion device according to the presentembodiment. FIG. 14 illustrates portions to which the first-typetransistor is applied in each block of the photoelectric conversiondevice illustrated in FIG. 10. When a block listed in the column ofblock names includes the first-type transistor, a symbol “circle (O)” isplaced in the column of the first-type transistor, and when a blocklisted in the column of block names does not include the first-typetransistor, a symbol “cross (X)” is placed in the column of thefirst-type transistor. First, by applying the first-type transistor tothe unit cell portion 1000, it is possible to reduce influence, on thePD, of a dark current (leak current) which occurs in the periphery ofthe element isolation portion. Furthermore, as described in the fifth toseventh embodiments, the first-type transistor is applied to a portionwhere noise may be superimposed on a signal of at least one of thecurrent source circuit 1003, the signal amplifier circuit 1004, and theAD converter circuit 1005 in the signal readout unit. The first-typetransistor is applied to a portion where noise may be superimposed onthe signals of the three circuits.

On the other hand, in one embodiment, the first-type transistor is notto be applied but the second-type transistor is to be applied to atransistor in a complete on-state, for example, a transistor thatfunctions as a switch in a circuit of a signal readout unit. Forexample, a control signal used for turning on and off a transistor thatfunctions as a switch is the ground voltage GND when the transistor is aP-type transistor and the power source voltage Vdd when the transistoris an N-type transistor. Since an even inversion region is generated inthe channel of the transistor to which such a control signal issupplied, a current is concentrated at the channel end near the elementisolation portion and hardly flows. Therefore, since the RTN is lesslikely to increase, the second-type transistor instead of the first-typetransistor can be applied. The semiconductor region 52 and thesemiconductor region 54 that have a conductivity opposite to thepolarity of the transistor are not provided to the second-typetransistor. That is, a p-n junction interface between the source and thedrain of the transistor and the semiconductor region 52 or thesemiconductor region 54 of the opposite conductivity is not formed. Itis therefore possible to suppress a reduction in the withstand voltagedue to a p-n junction. Further, when the effective channel width of atransistor is reduced, an on-resistance increases, which may cause areduction in the drive speed. Therefore, in a circuit where high speeddriving is used, the second-type transistor is applied instead of thefirst-type transistor. A circuit in which high speed driving is used maybe the vertical scanning circuit 1002, the ramp generation circuit 1006,the memory circuit 1007, the horizontal scanning circuit 1015, thecounter circuit 1008, the TG 1009, the signal processing circuit 1010,the signal output circuit 1011, or the like.

As illustrated in the present embodiment, in a device such as aphotoelectric conversion device in which a reduction of noisesuperimposed on a signal is desired, by applying the first-typetransistor in at least one circuit of the readout circuit portion, it ispossible to reduce noise superimposed on a signal.

Ninth Embodiment

In the present embodiment, a modified example of the inverting amplifier1112 in FIG. 11 illustrated in the fifth embodiment will be described.In the present embodiment, the inverting amplifier 1112 is changed froma single input amplifier to a differential amplifier. Other features ofthe present embodiment are the same as the features described in thefifth embodiment.

FIG. 15 is an equivalent circuit diagram illustrating a photoelectricconversion device according to the present embodiment. FIG. 15illustrates the inverting amplifier 1112. The inverting amplifier 1112is a differential amplifier. A P-type transistor 1501, a P-typetransistor 1502, an N-type transistor 1503, and an N-type transistor1504 form a differential pair. An N-type transistor 1506 forms a currentsource circuit. An N-type transistor 1505 functions as a switch used forturning on or off the current. A signal is input to the input end thatis the gate of the transistor 1504 as the voltage Vampi. A referencesignal Vref is input to other input ends. A difference between thevoltages input to the two input ends is amplified and output from theoutput end as the voltage Vampo. Here, as described in the fifthembodiment, when the RTN of the transistor deteriorates, the currentamount in the differential amplifier changes. At this time, when thecurrent flowing in the differential pair becomes unbalanced, the voltageVampo that is an output signal changes. Here, by forming thedifferential amplifier of the first-type transistor, it is possible toreduce RTN and improve signal quality. Further, the second-typetransistor is used for the transistor 1505 that functions as a switch.

The configuration of the present embodiment can also provide aphotoelectric conversion device with reduced noise.

Tenth Embodiment

In the present embodiment, an example of a photoelectric conversiondevice will be described. The photoelectric conversion device of thepresent embodiment is formed such that at least two semiconductorsubstrates used for stacking are electrically connected and stacked.Such a photoelectric conversion device is also referred to as astacked-type photoelectric conversion device. Here, the semiconductorsubstrate may also be referred to as a member or a chip.

FIG. 16 is a schematic diagram of a photoelectric conversion device 3000of the present embodiment and is a perspective exploded view of thephotoelectric conversion device 3000. A pixel region 3011 is provided inone semiconductor substrate 3010. A control unit 3021 and a signalprocessing unit 3022 are provided in a different semiconductor substrate3020. The pixel region 3011 corresponds to a photoelectric conversionunit to which the unit cell including a photoelectric conversion elementis arranged. The signal processing unit 3022 is provided with thesemiconductor memory described in the first embodiment or the like. Atleast a part of respective orthogonal projection of the control unit3021 and the signal processing unit 3022 to the semiconductor substrate3010 overlaps with the pixel region 3011. Note that the photoelectricconversion device 3000 of the present embodiment may further have asemiconductor substrate having another processing circuit or may havethree or more semiconductor substrates used for stacking.

The control unit 3021 may have a vertical scanning circuit that providesa drive signal to a pixel or a power source circuit. Further, thecontrol unit 3021 may include a timing generation circuit used fordriving the photoelectric conversion device, a reference signal supplycircuit configured to supply a reference signal to a converter circuit,or a horizontal scanning circuit used for reading out a signalsequentially from an amplifier circuit or a converter circuit.

The signal processing unit 3022 processes an electrical signal based onsignal charges generated in a pixel region. The signal processing unit3022 may include a noise removal circuit, an amplifier circuit, aconverter circuit, or an image signal processing circuit. The noiseremoval circuit is a correlated double sampling (CDS) circuit, forexample. The amplifier circuit is a column amplifier circuit, forexample. The converter circuit is an analog-to-digital conversion (ADC)circuit formed of a comparator and a counter, for example. The imagesignal processing circuit includes a memory device and a processor, forexample, and is configured to generate image data from ananalog-to-digital converted digital signal or perform image processingon image data.

The disclosure is also applicable to such a photoelectric conversiondevice in which a plurality of semiconductor substrates are stacked asdescribed in the present embodiment.

Eleventh Embodiment

FIG. 17 is a block diagram illustrating a configuration of an imagingsystem 3100 according to the present embodiment. The imaging system 3100of the present embodiment includes the photoelectric conversion device3104 described in the embodiments described above. Here, any of thephotoelectric conversion devices described above can be applied to thephotoelectric conversion device 3104. A specific example of the imagingsystem 3100 may be a digital still camera, a digital come coder, asurveillance camera, or the like. FIG. 10 illustrates an example of adigital still camera as the imaging system 3100.

The imaging system 3100 illustrated in FIG. 10 as an example has thephotoelectric conversion device 3104, a lens 3102 that captures anoptical image of a subject onto the photoelectric conversion device3104, an aperture 3103 used for changing the amount of light that haspassed through the lens 3102, and a barrier 3101 used for protecting thelens 3102. The lens 3102 and the aperture 3103 form an optical systemthat converges light onto the photoelectric conversion device 3104.

The imaging system 3100 has the signal processing unit 3105 thatprocesses output signals output from the photoelectric conversion device3104. The signal processing unit 3105 performs a signal processingoperation that performs various correction or compression on an inputsignal for output, if necessary. The imaging system 3100 further has abuffer memory unit 3106 used for temporarily storing image data and anexternal interface unit (external I/F unit) 3109 used for communicatingwith an external computer or the like. The imaging system 3100 furtherhas a storage medium 3111 such as a semiconductor memory used forperforming storage or readout of imaging data and a storage mediumcontrol interface unit (storage medium control I/F unit) 3110 used forperforming storage or readout on the storage medium 3111. Note that thestorage medium 3111 may be embedded in the imaging system 3100 or may beremovable. Further, communication from the storage medium control I/Funit 3110 to the storage medium 3111 or communication from the externalI/F unit 3109 may be wirelessly performed.

Furthermore, the imaging system 3100 has a general control/operationunit 3108 that performs various operations and controls the entiredigital still camera and a timing generation unit 3107 that outputsvarious timing signals to the photoelectric conversion device 3104 andthe signal processing unit 3105. Here, a timing signal or the like maybe input from the outside, and the imaging system 3100 has at least thephotoelectric conversion device 3104 and the signal processing unit 3105that processes output signals output from the photoelectric conversiondevice 3104. Note that, as described in the sixth embodiment, the timinggeneration unit 3107 may be embedded in the photoelectric conversiondevice. The general control/operation unit 3108 and the timinggeneration unit 3107 may be configured to perform a part or all of thecontrol function of the photoelectric conversion device 3104.

The photoelectric conversion device 3104 outputs an imaging signal tothe signal processing unit 3105. The signal processing unit 3105performs predetermined signal processing on an imaging signal outputfrom the photoelectric conversion device 3104 and outputs image data.Further, the signal processing unit 3105 uses an imaging signal togenerate an image. Note that the signal processing unit 3105 or thetiming generation unit 3107 may be embedded in the photoelectricconversion device. That is, the signal processing unit 3105 or thetiming generation unit 3107 may be provided on a substrate in whichpixels are arranged or may be provided in a different substrate asdescribed in FIG. 16. By forming the imaging system by using thephotoelectric conversion device of each embodiment described above, animaging system that can acquire a higher quality image can be realized.

Twelfth Embodiment

A moving unit of the present embodiment will be described by using FIG.18A and FIG. 18B and FIG. 19. FIG. 18A and FIG. 18B are schematicdiagrams illustrating a configuration example of the moving unitaccording to the present embodiment. FIG. 19 is a flow diagramillustrating an operation of the imaging system embedded in the movingunit according to the present embodiment. In the present embodiment, oneexample of an on-vehicle camera is illustrated as the imaging system. Inthe description below, the imaging device is any of the photoelectricconversion devices of respective embodiments described above.

FIG. 18A illustrates an example of a vehicle system and an imagingsystem mounted thereon. An imaging system 3201 includes imaging devices3202, image preprocessing units 3215, an integrated circuit 3203, andoptical systems 3214. Each of the optical systems 3214 captures anoptical image of a subject on the imaging device 3202. Each of theimaging devices 3202 converts an optical image of a subject captured bythe optical system 3214 into an electrical signal. Each of the imagepreprocessing units 3215 performs predetermined signal processing on asignal output from the imaging device 3202. The function of the imagepreprocessing unit 3215 may be embedded in the imaging device 3202. Theimaging system 3201 is provided with at least two sets of the opticalsystem 3214, the imaging device 3202, and the image preprocessing unit3215, and the output from the image preprocessing units 3215 ofrespective sets is input to the integrated circuit 3203.

The integrated circuit 3203 is an application specific integratedcircuit for the imaging system and includes an image processing unit3204 including a memory 3205, an optical ranging unit 3206, a parallaxcalculation unit 3207, an object recognition unit 3208, and an anomalydetection unit 3209. The image processing unit 3204 performs imageprocessing such as development process, defection correction, or thelike on the output signal from the image preprocessing unit 3215. Thememory 3205 stores primary storage of a captured image or a defectionposition of a captured image. The optical ranging unit 3206 performsfocusing or ranging of a subject. The parallax calculation unit 3207calculates a parallax information (a phase difference of parallaximages) from a plurality of image data acquired by the plurality ofimaging devices 3202. The object recognition unit 3208 recognizes asubject such as an automobile, a road, a traffic sign, a person, or thelike. In response to detection of an anomaly of the imaging device 3202,the anomaly detection unit 3209 reports the anomaly to a main controlunit 3213.

The integrated circuit 3203 may be implemented by dedicatedly designedhardware, may be implemented by a software module, or may be implementedby the combination thereof. Further, the integrated circuit 3203 may beimplemented by a Field Programmable Gate Array (FPGA), an ApplicationSpecific Integrated Circuit (ASIC), or the like, or may be implementedby the combination thereof.

The main control unit 3213 integrally controls the operation of theimaging system 3201, a vehicle sensor 3210, a control unit 3220, or thelike. Note that the imaging system 3201, the vehicle sensor 3210, andthe control unit 3220 may have separate communication interfaces withoutthe main control unit 3213, and a method of transmitting and receivingcontrol signals by respective components via the communication network(for example, CAN specification) may be employed.

The integrated circuit 3203 has a function of transmitting a controlsignal and a setting value to the imaging device 3202 in response toreceiving the control signal from the main control unit 3213 or by usinga control unit of the integrated circuit 3203.

The imaging system 3201 is connected to the vehicle sensor 3210 and cansense a traveling state of the vehicle, such as a vehicle speed, a yawrate, a steering angle, or the like, and a state of an environmentoutside the vehicle or another vehicle and an obstacle. The vehiclesensor 3210 also serves as a distance information acquisition unit thatacquires information on the distance from the parallax image to theobject. Further, the imaging system 3201 is connected to a drive supportcontrol unit 3211 that performs various drive supports such as automaticsteering, automatic patrol, collision prevention function, or the like.In particular, with respect to the collision determination function,estimation of a collision and determination of a collision againstanother vehicle and an obstacle are performed based on the sensingresult of the imaging system 3201 or the vehicle sensor 3210. Thereby,avoidance control when a collision is estimated or startup of a safetydevice at a collision is performed.

Further, the imaging system 3201 is connected to an alert device 3212that issues an alert to a driver based on the determination result in acollision determination unit. For example, when the determination resultof the collision determination unit indicates a high possibility ofcollision, the main control unit 3213 performs vehicle control to avoida collision or reduce damage by applying a break, moving back theaccelerator pedal, suppressing the engine power, or the like. The alertdevice 3212 performs an alert to a driver by sounding an alert such as asound, displaying alert information on a display unit screen such as acar navigation system, a meter panel, or the like, providing a vibrationto a sheet belt or a steering wheel, or the like.

In the present embodiment, the surrounding area of the vehicle, forexample, the area in front or rear is captured by the imaging system3201. FIG. 18B illustrates an arrangement example of the imaging system3201 when the area in front of the vehicle is captured by the imagingsystem 3201.

The two imaging devices 3202 are arranged in the front of the vehicle3200. Specifically, in terms of acquisition of the distance informationor determination of the possibility of collision between the vehicle3200 and the captured object, the center line is defined with respect tothe direction of traveling back and forth or the external shape (forexample, the vehicle width) of the vehicle 3200 as a symmetry axis andarrange the two imaging devices 3202 in a symmetrical manner withrespect to the symmetry axis. Further, in one embodiment, the imagingdevices 3202 is arranged so as not to block the driver's field of viewwhen the driver views the status outside the vehicle 3200 out of thedriver seat. It is preferable to arrange the alert device 3212 so as tobe easily viewed by the driver.

Next, a failure detection operation of the imaging device 3202 in theimaging system 3201 will be described by using FIG. 19. The failuredetection operation of the imaging device 3202 is performed inaccordance with steps S3310 to S3380 illustrated in FIG. 19.

Step S3310 is a step of performing a setting at startup of the imagingdevice 3202. That is, a setting used for the operation of the imagingdevice 3202 is transmitted from the outside of the imaging system 3201(the main control unit 3213, for example) or the inside of the imagingsystem 3201, and a capturing operation and a failure detection operationof the imaging device 3202 are started.

Next, in step S3320, a pixel signal is acquired from an effective pixel.Further, in step S3330, an output value from a failure detection pixelprovided for failure detection is acquired. The failure detection pixelhas a photoelectric conversion unit as with the effective pixel. Apredetermined voltage is written to the photoelectric conversion unit.The failure detection pixel outputs a signal corresponding to thevoltage written in the photoelectric conversion unit. Note that stepS3320 and step S3330 may be performed in reverse order.

Next, in step S3340, classification between an expected output value ofa failure detection pixel and an actual output value from a failuredetection pixel is performed. As a result of the classification in stepS3340, if there is a match between the expected output value and theactual output value, the process proceeds to step S3350, it isdetermined that the imaging operation is normally performed, and theprocess step proceeds to step S3360. In step S3360, a pixel signal on ascanning row is transmitted to the memory 3205 and temporarily stored.The process then returns to step S3320 to continue the failure detectionoperation. On the other hand, as a result of the classification in stepS3340, if there is no match between the expected output value and theactual output value, the process step proceeds to step S3370. In stepS3370, it is determined that there is an anomaly in the imagingoperation, and an alert is reported to the main control unit 3213 or thealert device 3212. The alert device 3212 causes a display unit todisplay that an anomaly has been detected. Then, in step S3380, theimaging device 3202 is stopped, and the operation of the imaging system3201 ends.

Note that, although the example in which the flowchart is looped on arow basis has been described in the present embodiment, the flowchartmay be looped on a multiple-row basis, or a failure detection operationmay be performed on a frame basis. Note that the reporting of the alertin step S3370 may be noticed to the outside of the vehicle via awireless network.

Further, although control for avoiding a collision to another vehiclehas been described in the present embodiment, the embodiment is alsoapplicable to automatic driving control for following another vehicle,automatic driving control for not going out of a traffic lane, or thelike. Furthermore, the imaging system 3201 is not limited to a vehiclesuch as a subject vehicle and can be applied to a moving unit (movingapparatus) such as a ship, an airplane, or an industrial robot, forexample. In addition, the imaging system can be widely applied to adevice which utilizes object recognition, such as an intelligenttransportation system (ITS), without being limited to moving units.

Thirteenth Embodiment

In the present embodiment, a manufacturing method of a photoelectricconversion device or a semiconductor memory will be described. Withregard to the present embodiment, reference to the drawings or thedetailed description of the embodiments described above will beappropriately made. The photoelectric conversion device has a StaticRandom Access Memory (SRAM)-type memory unit including a firsttransistor of the first conductivity type and a second transistor of thesecond conductivity type and a photoelectric conversion unit including aphotoelectric conversion element.

A manufacturing method of the photoelectric conversion device has stepsof preparing a semiconductor substrate having a first region, a secondregion, and a third region and forming grooves in the first region, thesecond region, and the third region by using a first mask pattern.Further, the manufacturing method has steps of forming a second maskpattern, performing implantation of impurity ions of the firstconductivity type, and forming a first element isolation portion, asecond element isolation portion, and a third element isolation portion.The manufacturing method further has steps of forming the firsttransistor and the second transistor and forming the photoelectricconversion element.

In the step of forming the second mask pattern, the second mask patternthat covers the groove formed in the first region and exposes the grooveformed in the second region and the groove formed in the third region isformed on the first mask pattern. In the step of performing theimplantation of impurity ions of the first conductivity type,implantation of impurity ions of the first conductivity type isperformed on the semiconductor substrate via the groove formed in thesecond region and the groove formed in the third groove by using thefirst mask pattern and the second mask pattern. In the step of formingthe first element isolation portion, the second element isolationportion, and the third element isolation portion, an insulator isembedded in the groove formed in the first region, the groove formed inthe second region, and the groove formed in the third region. The firstelement isolation portion in the first region, the second elementisolation portion in the second region, and the third element isolationportion in the third region are then formed. In the step of forming thefirst transistor and the second transistor, the first transistor isformed in the first region, and the second transistor is formed in thesecond region. In the step of forming the photoelectric conversionelement, the photoelectric conversion element is formed in the thirdregion. By having such steps, it is possible to manufacture aphotoelectric conversion device having small transistors whilesuppressing an increase in the number of steps.

Further, the manufacturing method may also have a step of forming athird transistor of the second conductivity type in the third region. Atthis time, the gate electrode of the first transistor extends on thefirst element isolation portion, the gate electrode of the secondtransistor extends on the second element isolation portion, and the gateelectrode of the third transistor extends on the third element isolationportion. Further, in the manufacturing method, the first mask patternmay be made of an inorganic material, and the second mask pattern may bemade of an organic material.

Further, the photoelectric conversion device includes a fourthtransistor of the first conductivity type and a fifth transistor of thesecond conductivity type and may have a processing circuit portion thatprocesses signals from the photoelectric conversion element. At thistime, the semiconductor substrate has a fourth region and a fifthregion. The manufacturing method then has steps of forming grooves inthe fourth region and the fifth region, forming a fourth elementisolation portion and a fifth element isolation portion, and forming thefourth transistor and the fifth transistor. In the step of forming thefourth element isolation portion and the fifth element isolationportion, an insulator is embedded in the groove formed in the fourthregion and the groove formed in the fifth region to form the fourthelement isolation portion in the fourth region and the fifth elementisolation portion in the fifth region. In the step of forming the fourthtransistor and the fifth transistor, the fourth transistor is formed inthe fourth region, and the fifth transistor is formed in the fifthregion. Here, the step of forming the second mask pattern is performedafter the step of forming the grooves in the fourth region and the fifthregion, and the second mask pattern covers the fourth region and thefifth region.

Further, the first to fifth element isolation portions may be elementisolation of the STI structure. Further, in the step of performingimplantation of impurity ions, the implantation of impurity ions isperformed obliquely with respect to the surface of the semiconductorsubstrate.

Further, the manufacturing method of the present embodiment can also beapplied to a semiconductor memory. For example, a semiconductor memoryhas a Static Random Access Memory (SRAM)-type unit cell including thefirst transistor of the first conductivity type and the secondtransistor of the second conductivity type. The manufacturing method ofthe semiconductor memory has steps of preparing a semiconductorsubstrate having the first region and the second region, forming thefirst groove and the second groove, and forming the second mask pattern.The manufacturing method further has steps of performing implantation ofimpurity ions, forming the first element isolation portion and thesecond element isolation portion, and forming the first transistor andthe second transistor. In the step of forming the first groove and thesecond groove, the first groove is formed in the first region and thesecond groove is formed in the second region by using the first maskpattern. In the step of forming the second mask pattern, the second maskpattern having an opening that covers the first groove and the exposesthe second groove is formed on the first mask pattern. In the step ofperforming the implantation of impurity ions, implantation of impurityions of the first conductivity is performed on the semiconductorsubstrate via the second groove by using the first mask pattern and thesecond mask pattern. In the step of forming the first element isolationportion and the second element isolation portion, an insulator isembedded in the first groove and the second groove to form the firstelement isolation portion having the first groove and the second elementisolation portion having the second groove. The step of forming thefirst transistor and the second transistor has a step of forming thefirst transistor in the first region and forming the second transistorin the second region. By having such steps, it is possible tomanufacture a semiconductor memory having small transistors whilesuppressing an increase in the number of steps.

The photoelectric conversion device of the aspect of the embodiments mayfurther have a color filter or a micro-lens or may be configured to beable to acquire various information such as distance information. Forexample, a plurality of photoelectric conversion elements may beincluded in one input node, and a single micro-lens may be commonlyprovided to a plurality of photoelectric conversion elements. Further,the amplification transistor forming a portion of the source followercircuit may form a portion of an AD convertor. Specifically, a part of acomparator included in the AD convertor may be formed of theamplification transistor. Further, some components of the comparator maybe provided to another semiconductor substrate. Further, a unit circuitmay have no transfer transistor, and the photoelectric conversionelement may be directly connected to the input node. Furthermore, acharge drain portion such as an overflow drain may be provided.

The disclosure is not limited to the embodiments described above, andvarious modifications are possible. For example, an example in which apart of the configuration of any of the embodiments is added to anotherembodiment or an example in which a part of the configuration of any ofthe embodiments is replaced with a part of the configuration of anotherembodiment is one of the embodiments of the disclosure. Although theexample of a semiconductor memory, a photoelectric conversion device, orthe like have been described in the embodiments described above, thestructure according to the transistor of the aspect of the embodimentsis also applicable to other devices. Any of the embodiments describedabove merely illustrates embodied examples in implementing thedisclosure, and the technical scope of the disclosure is not to beconstrued in a limiting sense by these examples. That is, the aspect ofthe embodiments can be implemented in various forms without departingfrom the technical concept thereof or the primary features thereof.

The aspect of the embodiments can improve characteristics of atransistor.

While the disclosure has been described with reference to exemplaryembodiments, it is to be understood that the disclosure is not limitedto the disclosed exemplary embodiments. The scope of the followingclaims is to be accorded the broadest interpretation so as to encompassall such modifications and equivalent structures and functions.

This application claims the benefit of Japanese Patent Application No.2018-196846, filed Oct. 18, 2018, and Japanese Patent Application No.2019-089187, filed May 9, 2019, which are hereby incorporated byreference herein in their entirety.

What is claimed is:
 1. A memory comprising a Static Random Access Memory(SRAM)-type unit cell including a first transistor of a firstconductivity type and a second transistor of a second conductivity type,wherein the first transistor is arranged in an active region of asemiconductor substrate, wherein the active region overlaps with a gateelectrode of the first transistor and includes a portion located betweena source and a drain of the first transistor, wherein the portion isarranged across a first position, a second position, and a thirdposition aligning in order along a channel width direction of the firsttransistor, wherein the portion includes a first semiconductor region ofthe second conductivity type arranged in the first position and a secondsemiconductor region of the second conductivity type arranged in thesecond position, wherein an impurity concentration of the firstsemiconductor region is higher than an impurity concentration of thesecond semiconductor region, wherein the unit cell includes a thirdtransistor of the first conductivity type and a fourth transistor of thesecond conductivity type, wherein the first transistor and the thirdtransistor function as a load transistor, and wherein the secondtransistor and the fourth transistor function as a driver transistor. 2.The memory according to claim 1, wherein a channel of the firsttransistor is formed at the second position.
 3. The memory according toclaim 1, wherein, in the portion, a third semiconductor region of thesecond conductivity type is arranged at the third position, and whereinan impurity concentration of the third semiconductor region is higherthan the impurity concentration of the second semiconductor region. 4.The memory according to claim 1, wherein the first conductivity is aP-type, and the second conductivity type is an N-type.
 5. The memoryaccording to claim 1, wherein when the gate electrode of the firsttransistor is turned on, each of the impurity concentration of the firstsemiconductor region and the impurity concentration of the secondsemiconductor region is an impurity concentration at which a channel isformed at the second position.
 6. The memory according to claim 1,wherein the impurity concentration of the first semiconductor region andthe impurity concentration of the second semiconductor region satisfyC1≥2×C2, where C1 denotes the impurity concentration of the firstsemiconductor region and C2 denotes the impurity concentration of thesecond semiconductor region.
 7. The memory according to claim 6, whereinthe impurity concentration of the first semiconductor region and theimpurity concentration of the second semiconductor region satisfyC1≥10×C2.
 8. The memory according to claim 1, wherein the active regionis adjacent to an element isolation portion having a trench in a planview, and wherein the gate electrode of the first transistor extends onthe element isolation portion.
 9. The memory according to claim 8,wherein the first position is located between a side face of the trenchand the second position.
 10. A photoelectric conversion devicecomprising: the memory according to claim 1; and a photoelectricconversion unit in which a photoelectric conversion element is arranged,wherein the memory and the photoelectric conversion unit are on a singlesubstrate.
 11. A photoelectric conversion device comprising: the memoryaccording to claim 1; and a photoelectric conversion unit in which aphotoelectric conversion element is arranged, wherein a substrate onwhich the memory is provided and a substrate on which the photoelectricconversion unit is provided are stacked.
 12. A system comprising: thephotoelectric conversion device according to claim 11; and a signalprocessing unit that processes a signal from the photoelectricconversion device.
 13. A moving unit comprising: the photoelectricconversion device according to claim 11; and an acquisition unit thatacquires distance information on a distance to an object, from parallaxinformation based on signals from the photoelectric conversion device;and a control unit that controls the moving unit based on the distanceinformation.
 14. A photoelectric conversion device comprising: a unitcell portion in which a plurality of unit cells are arranged, whereineach of the plurality of unit cells has a photoelectric conversionelement; and a readout unit used for reading out a signal from the unitcell portion, and arranged in a portion other than the unit cellportion, wherein the readout unit has at least one first transistor of afirst conductivity type, wherein the first transistor is arranged in anactive region of a semiconductor substrate, wherein the active regionoverlaps with a gate electrode of the first transistor and includes afirst portion located between a source and a drain of the firsttransistor, wherein the first portion is arranged across a firstposition, a second position, and a third position aligned in order alonga channel width direction of the first transistor, wherein the firstportion includes a first semiconductor region of the second conductivitytype arranged at the first position and a second semiconductor region ofthe second conductivity type arranged at the second position, andwherein an impurity concentration of the first semiconductor region ishigher than an impurity concentration of the second semiconductorregion.
 15. The photoelectric conversion device according to claim 14,wherein the readout unit includes at least one of a current sourcecircuit, a signal amplifier circuit, and an analog-to-digital convertercircuit, and wherein the at least one of the current source circuit, thesignal amplifier circuit, and the analog-to-digital converter circuitincludes the first transistor.
 16. The photoelectric conversion deviceaccording to claim 14, wherein the readout unit includes at least acurrent source circuit and an analog-to-digital converter circuit, andwherein the analog-to-digital conversion circuit includes a comparatorhaving another current source circuit, and the current source circuitand the another current circuit include the first transistor.
 17. Thephotoelectric conversion device according to claim 14, wherein thereadout unit has at least a second transistor of the first conductivitytype, and the second transistor is arranged in another active region inthe semiconductor substrate, wherein the active region overlaps with agate electrode of the second transistor and includes a second portionlocated between a source and a drain of the second transistor, whereinthe second portion is arranged across a fourth position, a fifthposition, and a sixth position aligned in order along a channel widthdirection of the second transistor, wherein the second portion includesa fourth semiconductor region of the second conductivity type arrangedat the fourth position and a fifth semiconductor region of the secondconductivity type arranged at the fifth position, and wherein the fourthsemiconductor region and the fifth semiconductor region have a sameimpurity concentration.
 18. The photoelectric conversion deviceaccording to claim 14, wherein the readout unit has at least a secondtransistor of the first conductivity type, and the second transistor isarranged in another active region in the semiconductor substrate,wherein the active region overlaps with a gate electrode of the secondtransistor and includes a second portion located between a source and adrain of the second transistor, wherein the second portion is arrangedacross a fourth position, a fifth position, and a sixth position alignedin order along a channel width direction of the second transistor,wherein the second portion includes a fourth semiconductor region of thesecond conductivity type arranged at the fourth position and a fifthsemiconductor region of the second conductivity type arranged at thefifth position, and wherein the second conductivity is a P-type, and adifference between a maximum and a minimum of the impurityconcentrations of the first semiconductor region and the secondsemiconductor region is smaller than a difference between the impurityconcentration of the first semiconductor region and the impurityconcentration of the second semiconductor region.
 19. The photoelectricconversion device according to claim 14, wherein the unit cell includesa transfer transistor that transfers charges from the photoelectricconversion element and an amplification transistor that outputs a signalbased on the charges, and wherein each of the transfer transistor andthe amplification transistor is the first transistor.
 20. A systemcomprising: the photoelectric conversion device according to claim 14;and a processing unit that processes a signal from the photoelectricconversion device.
 21. A moving unit comprising: the photoelectricconversion device according to claim 14; an acquisition unit thatacquires distance information on a distance to an object, from parallaxinformation based on signals from the photoelectric conversion device;and a control unit that controls the moving unit based on the distanceinformation.
 22. A moving unit comprising: a photoelectric conversiondevice; and an acquisition unit that acquires distance information on adistance to an object, from parallax information based on signals fromthe photoelectric conversion device; and a control unit that controlsthe moving unit based on the distance information, wherein thephotoelectric conversion device comprises: a memory; and a photoelectricconversion unit in which a photoelectric conversion element is arranged,wherein a substrate on which the memory is provided and a substrate onwhich the photoelectric conversion unit is provided are stacked, whereinthe memory comprising a Static Random Access Memory (SRAM)-type unitcell including a first transistor of a first conductivity type and asecond transistor of a second conductivity type, wherein the firsttransistor is arranged in an active region of a semiconductor substrate,wherein the active region overlaps with a gate electrode of the firsttransistor and includes a portion located between a source and a drainof the first transistor, wherein the portion is arranged across a firstposition, a second position, and a third position aligning in orderalong a channel width direction of the first transistor, wherein theportion includes a first semiconductor region of the second conductivitytype arranged in the first position and a second semiconductor region ofthe second conductivity type arranged in the second position, andwherein an impurity concentration of the first semiconductor region ishigher than an impurity concentration of the second semiconductorregion.